Multi-port packet processor

ABSTRACT

A multi-port packet processor on an integrated circuit provides an efficient means to interface multiple high-speed packet-based communications channels. The multi-port packet processor includes multiple port processors. Each port processor can include a channel interface for coupling to a respective communications channel, a channel processor for processing the data packets received through the channel interface, and an interprocessor communications interface for providing communication between the port processors. The channel interface can be designed to process data packets using a particular set of packet-based protocols. Alternatively, the channel interface can be designed having programmable controls to allow processing of data packets using a selected set, from a number of possible sets, of packet-based protocols.

[0001] This application claims the benefit of U.S. provisionalApplication No. 60/057,813, filed Sep. 4, 1997, which is incorporatedherein by reference.

BACKGROUND OF THE INVENTION

[0002] This invention relates generally to a computer network, and inparticular to a multi-port packet processor for processing communicationwithin a computer network.

[0003] A computer network is an interconnection of various computers bya network of communication devices (often utilizing more than onecommunications protocols). One such example of a computer network is theInternet that interconnects personal computers and servers throughtelephone lines and high-speed transmission lines. Other examples ofcomputer network include a local area network (LAN), a wide area network(WAN), and other special purpose networks including networks based uponprotocols such as RS-485 instrumentation protocol and Universal SerialBus (USB). The interconnection of (relatively) smaller devices into anetwork facilitates transactions of large scale organizations, allowsfor efficient dissemination of information, provides for communicationsbetween various devices within the network, and allows for sharing ofresources and data.

[0004]FIG. 1 illustrates a conventional computer network 100. Network100 includes a number of user computers 110 and servers 112interconnected together through hubs 120, switches 122, and a router124. The user computers 110 and servers 112 connect to the networkthrough respective Network Interface Cards (NICs, not shown). The NICsreceives data (i.e., in bytes) from the computer or server and formsdata packets for transmission on the network transmission line. Thehubs, switches, and routers receive the data packets and direct thepackets to the proper destination. At the destination, another NICreceives the data packets and translates the packets into bytes usableby the computer or server. The interconnection between a pair of devicescan be an Unshielded Twisted-Pair (UTP) cable (such as a telephoneline), a coaxial cable, a fiber optic cable, or other transmissionmediums.

[0005] A network can be viewed as being composed of various layers, witheach layer performing a defined function. Each layer communicates withthe layer above and/or below it. Furthermore, each layer can beimplemented with hardware or software, or a combination of both.

[0006]FIG. 2 illustrates the various layers of an Open SystemInterconnection (OSI) computer network 200. Computer network 200 iscomposed of seven layers including: (1) a physical layer 210, (2) a datalink layer 212, (3) a network layer 214, (4) a transport layer 216, (5)a session layer 218, (6) a presentation layer 220, and (7) anapplication layer 222. The physical layer 210 transmits bit streamsacross the physical transmission system. The data link layer 212provides for a reliable data transmission. The network layer 214 routesdata from one network node to another. The transport layer 216 providesdata transfer between two users at a predetermined level of quality. Thesession layer 218 manages the data exchange. The presentation layer 220presents information to the users in a meaningful manner. Finally, theapplication layer 222 monitors and manages the computer network 200.

[0007] Communication between the various layers is governed by a set ofprotocols. The layers and protocols, in turn, define the architecture ofa network. Conventionally, many diverse protocols exist that areincompatible with other protocols. Some protocols are adopted by largemanufacturers to differentiate their products from those of othermanufacturers, or for other reasons. Thus, although a product from oneproduct line can communicate with other products from the same productline, it is often incompatible with other products from othermanufacturers. Examples of network protocols include Integrated ServicesData Network (ISDN), Ethernet, Fast Ethernet, Gigabit Ethernet,Asynchronous Transfer Mode (ATM), Copper Distributed Data Interface(CDDI), Fiber Distributed Data Interface (FDDI) and Fiber Channel (alsoknown as P1394).

[0008] Interconnectivity and interoperability between (compatible andincompatible) networks, or segments of a network, can be provided byinterconnection devices (e.g., routers, hubs, bridges, gateways). Withthe proliferation of networks in the marketplace, and the numerousprotocols in used, the interconnection devices become an integral partof many networks. Referring to FIG. 2, a hub 230, which operates on thephysical layer 210, is used to connect segments of the same network toform an extended network. A hub is also referred to as a repeater. Abridge 232, which operates on the data link layer 212, is used toconnect compatible (or nearly compatible) LANs. A router 234, whichoperates on the network layer 214, connects two network segments to formone large network. Finally, a gateway 236, which operates on any layerat or above the network layer 214, connects an internal network to anexternal network. The gateway 236 is the most complex but also mostflexible interconnection device, as it allows for different protocols atany or all layers on which it operates.

[0009] As networks become larger and faster, new applications requiringgreater bandwidth become feasible. Examples of high bandwidthapplications include video on demand, video games, and others. Theseapplications place stress on various parts of the network architecture,including the NICs, the communications channel, and the interconnectiondevices (e.g., the servers). A bottleneck is often created in the datacommunications system, with one likely area of congestion being the maincomputer bus of the server.

[0010] From the above, it can be noted that a processor that facilitateshigh-speed data communications is needed.

SUMMARY OF THE INVENTION

[0011] According to the invention, a multi-port packet processorprovides an efficient mechanism to interface multiple high-speedpacket-based communications channels to each other. The multi-portpacket processor is implemented within an integrated circuit for lowcost, high performance, and improved reliability.

[0012] The multi-port packet processor includes multiple portprocessors. Each port processor can include a channel interface forcoupling to a respective communications channel and a channel processorfor processing the packets received through the channel interface. Thechannel interface can be designed to process packet-based communicationfrom a channel using a particular set of packet-based protocols.Alternatively, the channel interface can be designed having programmablecontrol such that the channel interface can be configured to send andreceive packets using a selected set (from a number of possible sets) ofpacket-based protocols.

[0013] Each port processor can further include an interprocessorcommunications interface coupled to at least one other port processorfor providing communication between the port processors.

[0014] In a specific embodiment, the port processor is capable ofprocessing multiple communications channels concurrently. Thecommunications channels can have identical packet-based protocols ordifferent packet-based protocols.

[0015] The multi-port packet processor can be used in a variety ofapplications. In one application, the multi-port packet processorfunctions as a local area network (LAN) processor and provides thefunctions typically provided by a LAN server. In another application,the multi-port packet processor functions as a disk storage processorand manages data transfer between various storage devices.

[0016] The invention will be better understood by reference to thefollowing detailed description with accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIG. 1 illustrates a conventional computer network.

[0018]FIG. 2 illustrates various layers of an Open SystemInterconnection (OSI) computer network.

[0019]FIG. 3 is a simplified block diagram illustrating a local areanetwork (LAN) channel communications hub.

[0020]FIG. 4A is a block diagram of one embodiment of an integratedmulti-port processor.

[0021]FIG. 4B is a block diagram of another embodiment of an integratedmulti-port processor.

[0022]FIG. 4C is a block diagram of yet another embodiment of anintegrated multi-port processor.

[0023]FIG. 5 shows a specific application wherein a multi-port processoris used to process data transfer in a mass storage environment.

[0024]FIG. 6 shows another specific application wherein a more than oneof multi-port processors are configured as a two-dimensional grid packetserver.

[0025]FIG. 7 shows yet another specific application wherein a more thanone of multi-port processors are configured as a three-dimensional gridpacket server.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0026] LAN Hub

[0027]FIG. 3 is a simplified block diagram illustrating a local areanetwork (LAN) channel communications hub 300. LAN hub 300 includes anumber of packet-based protocol channels 310 coupled to a multi-portprocessor 320. LAN hub 300 can correspond to hub 120 in the networkshown in FIG. 1. Channels 310 (shown symbolically as blocks in FIG. 3)include different LAN channels such as ISDN, Ethernet, Fast Ethernet,Gigabit Ethernet, ATM, CDDI, FDDI, or P1394 (also known as Firewire)channels, or other communications channels. Furthermore, the variouschannels 310 shown in FIG. 3 may utilize different types of protocols.For example, some channels 310 may support mass storage communicationsprotocols (e.g., Small Computer Systems Interface SCSI) while otherchannels 310 may support LAN protocols (e.g., Ethernet).

[0028] Multi-Port Processor

[0029]FIG. 4A is a block diagram of one embodiment of an integratedmulti-port processor 400. Multi-port processor 400 can operate asmulti-port processor 320 in FIG. 3. Multi-port processor 400 efficientlycontrols and manages communication through multiple packet-basedprotocol channels 310. Conventionally, this function is performed by alarger device, such as a LAN server.

[0030] Multi-port processor 400 includes a number of port processors410. In an embodiment shown in FIG. 4A, there are four port processors410 and each port processor 410 includes eight circuits. The eightcircuits include: (1) input/output (I/O) buffers 420, (2) I/Ocontrollers 422, (3) an interprocessor communications circuit 424, (4) achannel processor 426, (5) a cache controller 428, (6) an internalmemory 430, (7) a memory controller 432, and (8) memory buffers 434.Each of the circuits is further discussed below.

[0031] I/O buffers 420 provide buffering of data packets received from,and to be transmitted on, the communications channel. I/O controllers422 direct reception and transmission of the data packets and caninclude a temporary storage element for queuing packets and performingdata processing tasks such as encryption/decryption, format conversionand error correction/detection operations upon the data of one or morepackets.

[0032] Interprocessor communications circuit 424 can include aninterrupt controller for triggering specific real-time actions inresponse to either network conditions, higher level network controlcommands, or other port processors and an interprocessor I/O circuit.The interprocessor I/O circuit can include clock timer counters andother circuits.

[0033] Channel processor 426 directs the operation of port processor 410and can be implemented as a microprocessor, a microcomputer, amicrocontroller, an applications specific integrated circuit (ASIC), adigital signal processor (DSP), a finite state machine (such as aregister store, Field Programmable Gate Array-FPGA, or ComplexProgrammable Logic Device-CPLD), or similar circuits. Cache controller428 can include a cache (i.e., a first level cache). Internal memory 430provides storage for data and program codes and can be implemented as arandom-access memory (RAM), a dynamic random-access memory (DRAM), aread-only memory (ROM), a FLASH memory, other similar devices, or acombination of the above. Additionally, internal memory 430 can includea boot ROM (or possibly a boot FLASH memory) for initializing portprocessor 410. In one embodiment, internal memory 430 can include enoughmemory (i.e., enough RAM, ROM, and other memories) such that an externalmemory is not required. Memory controller 432 directs the exchange ofdata between port processor 410 and an external memory. Memory buffers434 provides buffering of data received from, and to be transmitted to,the external memory.

[0034] As shown in FIG. 4A, multi-port processor 400 further includes asupport circuit 436 for each port processor 410. In particular, supportcircuits 436a, 436b, 436c, and 436d couple to port processors 410a,410b, 410c, and 410d, respectively. Support circuit 436 can include I/Ocircuits, a memory, drivers, and other circuits. Support circuit 436facilitates communication between port processor 410 and the one or morecommunications channels associated with the port processor. Supportcircuits 436 can provide analog conversion for different physical signalstates communicating bits on the coupled communication channel. Forexample, this analog conversion can transform logic signal (e.g., forzero and one) to drive a laser which requires a different signalingconvention.

[0035] Communication Mechanisms

[0036] Referring to the embodiment shown in FIG. 4A, each port processor410 includes three communications mechanisms: (1) a channel interface440, (2) an external memory interface 442, and (3) an internal processor(or interprocessor) communications interface 444. Channel interface 440includes I/O buffers 420 and I/O controllers 422. External memoryinterface 442 includes memory controller 432 and memory buffers 434.Interprocessor communications interface 444 includes interprocessorcircuit 424.

[0037] Channel interface 440 can be designed to process packet-basedcommunication from a channel using a particular set of packet-basedprotocols. Alternatively, channel interface 440 can be designed havingprogrammable controls such that the channel interface can be configuredto send and receive packets using a selected set (from a number ofpossible sets) of packet-based protocols. The programmability can beprovided by implementing channel interface 440 (i.e., I/O controller424) with a processor, a finite state machine, or other suitabledevices. The processor or finite state machine can be designed with thecapability to initiate and operate using one of various sets of states.Such processors or finite state machines may either be fixed program orreconfigurably programmable.

[0038] An interprocessor communications network is made up of multipleinterprocessor communications interfaces 444. The interprocessorcommunications network can interconnect all port processors 410, or asubset of port processors 410. Furthermore, the interprocessorcommunications network includes a communications mechanism that caninclude packet data transfer and (possibly) transfer command/statussignals.

[0039] The interprocessor communications network allows the various portprocessors 410 to coordinate and efficiently manage communicationbetween two or more communications channels. For example, one portprocessor 410 may be assigned to one channel utilizing a particular setof protocols and another port processor 410 may be assigned to anotherchannel utilizing the same or a different set of protocols. Theinterprocessor communications network allows for communication betweentwo (possibly incompatible) channels. In this manner, the interprocessorcommunications network behaves like bridge 232 or router 234 as shown inFIG. 2.

[0040] Note the shape of the port processors 410a, 410b, 410c and 410d.The circuits are shown as roughly rectangular, which is the approximateshape they would possess in an integrated circuit layout. The individualcomponents of the port processors would not necessarily be approximatelythe same size, but are shown this way for diagrammatic convenience. Theindividual components of the port processors would however beapproximately rectangular.

[0041] Further note the arrangement of the port processors 410a, 410b,410c and 410d. They are arranged so that the long axis orientation isflipped for neighboring port processors. Preferred embodiments includepairs of port processors sharing the same orientation and neighboringpairs being flipped. Another preferred embodiment where the portprocessors do not possess external memory interfaces include only twogroups of port processors in one integrated circuit, where each groupshares an orientation and one group's orientation is flipped from theother group's orientation.

[0042] Further note the placement of the interprocessor communicationsinterface 444. These circuits are optimally placed within the portprocessor so as to minimize the total wire length required.Accomplishing this requires knowledge of which port processorarrangements are to be implemented. Where there is to be orientationflipping, either the placement should be essentially in the middle ofthe port processor rectangular shape, or it should be split into twocomponents, which are located at approximately equal distances from thecenter of the port processor long axis.

[0043] Port Processing

[0044] In one embodiment, each port processor 410 has the capability tosimultaneously interface with one or more packet-based protocolchannels. High-speed packet transfers between these channels by one portprocessor 410 are accommodated by the channel interface communicationsmechanism (i.e., provided by I/O buffers 420 and I/O controllers 422)within that port processor 410. This transfer activity is controlled bythe corresponding channel processor 426 within that port processor 410.This provides for an efficient, low overhead transfer mechanism betweenthe “local” channels within each port processor 410.

[0045] In another embodiment, communication between channels coupled todifferent port processors 410 is provided by the interprocessorcommunications network. In this embodiment, packet data transfersproceed unimpeded while command and status transactions occurconcurrently. Packet data transfer occurs on physically separatechannels from command and status information transfers. Neither isslowed by the transfer characteristics of the other.

[0046] Port processor 410 can be designed to operate on one or morelayers (similar to the design of gateway 236). Referring to FIG. 2, portprocessor 410 can be designed to operate on physical layer 210, datalink layer 212, network layer 214, or a combination of these layers.

[0047] Packet transfer and conversion can be partitioned into separatecomponent activities of block data transfer and block data processing.These separable activities are preferably performed by distinctconcurrently operating mechanisms, which by and large do not interferewith each other. The block data transfer is further preferably isolatedfrom disruptive intrusions caused by the communication of control andstatus information through the use of separate communications mechanismsfor such activities.

[0048] Modular Design

[0049]FIG. 4B illustrates the flexibility in the design of a multi-portprocessor because of the modular design of the port processor. Amulti-port processor 402 can interface and process data transmissionsusing various packet-based protocols. Alternatively, a multi-portprocessor 402 may interface and process just one data transmission usingjust one packet-based protocol. As shown in FIG. 4B, port processors412a, 412b, 412c, and 412d include channel interfaces 450a, 450b, 450c,and 450d, respectively. Each channel interface 450 can be designed witha particular set of I/O buffers and I/O controllers corresponding to thepacket-based protocols to be utilized. Alternatively, as describedabove, each channel interface 450 can have programmable controls toallow processing of packets using a selected set of protocols from amonga number of sets of protocols. For example, one channel interface 450 ofmulti-port processor 402 can support ISDN or Ethernet, another channelinterface 450 can support ATM, and another channel interface 450 cansupport SCSI. As another example, a four port multi-port packetprocessor can include one Gigabit Ethernet port processor, one FastEthernet port processor, one Ethernet port processor, and one FiberChannel port processor interfacing to a disk farm.

[0050]FIG. 4C is a block diagram illustrating a multi-port processor 404including six port processors 410. Multi-port processor 404 is differentin configuration than multi-port processor 400 (see FIG. 4A) whichincludes only four port processors 410. As these examples show, themulti-port processor can be designed to include any number of portprocessors, including two, four, six, eight, sixteen, thirty-two, or anyother number. Although an even number of port processors can providecertain advantages (e.g., layout efficiency), odd number of portprocessors can also be, designed and utilized. Again, as describedabove, each port processor 410 can include a different channel interface(i.e., different set of I/O buffers and I/O controllers) or aprogrammable channel interface.

[0051] Referring to FIGS. 4A through 4C, each port processor is shownhaving a single channel interface. However, a port processor can bedesigned to include any number channel interfaces. Furthermore, eachport processor can be designed with a channel interface without regards(i.e., individually and independently) to the other port processorswithin the multi-port processor. For example, a multi-port processor canbe designed such that one port processor includes one channel interface,a second port processor includes two channel interfaces, a third portprocessor includes three channel interfaces, and so on. Examples of thisinclude multiple RS-485 channels support GPIB instrumentation protocolsand dual USB channels.

[0052] Other Applications of Multi-Port Processor

[0053]FIG. 5 shows a specific application wherein a multi-port processor500 is used to process data transfer in a mass storage environment. Thisenvironment is commonly referred to as a “disk farm”. The disk farmincludes a number of storage devices (e.g., hard disk drives, tapedrives, CD drives, floppy disk drives, or other storage devices). Eachstorage device couples to multi-port processor 500 through a respectivecommunications channel 510 or 512. An example of a disk farm is aRedundant Disk RAID system that provides mass disk storage with a levelof redundancy for increased system reliability. Conventionally, thisdata transfer control requires a complex device.

[0054]FIG. 6 shows another specific application wherein a more than oneof multi-port processors 600 are configured as a two-dimensional gridpacket server 610. FIG. 6 shows a four by four grid of multi-portprocessors 600. However, other dimensions can also be used, and symmetryis generally not required. In one embodiment, a portion of thepacket-based communications channels of each multi-port processor 600 isused for communication in the row and column in which the particularmulti-port processor 600 is located. These channels may have differentprotocols. For example, one channel may employ the P1394 protocol toprovide higher bandwidth within server 610. The remaining channels canbe used for providing communication with the network.

[0055]FIG. 7 shows yet another specific application wherein a more thanone of multi-port processors 700 are configured as a three-dimensionalgrid packet server 710. FIG. 7 shows a four-by-four-by-four grid ofmulti-port processors 700. However, other dimensions can also be usedand symmetry is again generally not required. In one embodiment, aportion of the packet-based communications channels of each multi-portprocessor 700 is used for communication in the row, column, and quadrantin which the particular multi-port processor 700 is located. Thesechannels may have different protocols.

[0056] The structures shown in FIGS. 6 and 7 can be extended to afour-dimensional array of multi-port processors, a five-dimensionalarray of multi-port processors, or an M-dimensional array of multi-portprocessors, where M is any integer.

[0057] The previous description of specific embodiments is provided toenable any person skilled in the art to make or use the presentinvention. The various modifications to these embodiments will bereadily apparent to those skilled in the art, and the generic principlesdefined herein may be applied to other embodiments without the use ofthe inventive faculty. For example, each port processor can includedifferent circuits than that shown in FIGS. 4A through 4C, depending onthe functionality required. Thus, the present invention is not intendedto be limited to the embodiments shown herein but is to be accorded thewidest scope consistent with the principles and novel features disclosedherein and as defined by the following claims.

What is claimed is:
 1. A multi-port packet processor comprising: morethan one of port processors, each port processor comprising a channelinterface for coupling to at least one communications channel, and achannel processor coupled to the channel interface, the channelprocessor processing data packets received or transmitted through thecommunications channel; and wherein the port processors are implementedwithin one integrated circuit.
 2. The multi-port packet processor ofclaim 1 further comprising: more than one support circuit, one supportcircuit coupled to each of the port processors, wherein the supportcircuits facilitate communication with respective communicationschannels.
 3. The multi-port packet processor of claim 2 wherein thesupport circuit of one or more of the port processors provides analogconversion circuitry for different physical signal states communicatingbits on the coupled communication channel.
 4. The multi-port packetprocessor of claim 1 wherein each port processor further comprises aninterprocessor communications interface coupled to the channel processorand the interprocessor communications interfaces to at least one otherport processor.
 5. The multi-port packet processor of claim 1 whereinthe channel interface of at least one port processor supports more thanone packet-based protocol.
 6. The multi-port packet processor of claim 5wherein the channel interface can be programmably reconfigured toprocess data packets using a selected protocol from a set of more thanone packet-based protocol.
 7. The multi-port packet processor of claim 5wherein the processed packet-based protocols include at least one of anIntegrated Services Data Network (ISDN), an Ethernet, a Fast Ethernet, aGigabit Ethernet, an Asynchronous Transfer Mode (ATM), a CopperDistributed Data Interface (CDDI), a Fiber Distributed Data Interface(FDDI), a RS-485 GPIB, and a P1384.
 8. The multi-port packet processorof claim 1 as used in a local area network.
 9. The multi-port packetprocessor of claim 1 as used in a wide area network.
 10. The multi-portpacket processor of claim 1 as used in a disk storage environment. 11.The multi-port packet processor of claim 1 comprising four portprocessors.
 12. The multi-port packet processor of claim 1 comprisingeight port processors.
 13. The multi-port packet processor of claim 1wherein each port processor further includes a memory coupled to thechannel processor.
 14. The multi-port packet processor of claim 1wherein the port processors are arranged in substantially rectangularstrips possessing a short axis in the integrated circuit.
 15. Themulti-port packet processor of claim 14 wherein the port processors areflipped about the short axis for neighboring port processors.
 16. Themulti-port packet processor of claim 14 wherein the port processors arearranged as pairs of port processors wherein the pairs of adjacent portprocessors are flipped about the short axis for neighboring pairs ofport processors.
 17. A local area network (LAN) processor comprising:more than one port processors, each port processor coupled to arespective communications channel, each port processor providingpacket-based processing using respective packet-based protocols; whereinall of the port processors are implemented within one integratedcircuit.
 18. The multi-port processor of claim 1 wherein the portprocessors operate on packets at a physical layer.
 19. The multi-portprocessor of claim 1 wherein the port processors further operate onpackets at a data link layer.
 20. The multi-port processor of claim 1wherein the port processors further operate on packets at a networklayer.
 21. The multi-port processor of claim 1 wherein the channelinterface of at least one of the port processors couples to more thanone communications channel.
 22. A grid array processor comprising: amore than one of multi-port packet processors arranged in atwo-dimensional array, each multi-port packet processor coupled to atleast one other multi-port packet processor, each multi-port packetprocessor including a more than one of port processors, each portprocessor coupled to at least one respective communications channel,each port processor providing packet-based processing using respectivepacket-based protocols; wherein each multi-port packet processor isimplemented within one integrated circuit.
 23. A multi-dimensional gridarray processor comprising: more than one of multi-port packetprocessors arranged in a multi-dimensional array, each multi-port packetprocessor coupled to at least one other multi-port packet processor,each multi-port packet processor including more than one portprocessors, each port processor coupled to at least one respectivecommunications channel, each port processor providing packet-basedprocessing using respective packet-based protocols; wherein eachmulti-port packet processor is implemented in one integrated circuit.